| nSys - ASIC Engineer |
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| Written by admin |
| Monday, 20 July 2009 02:54 |
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You will work from specifications and take the design through HDL coding, testbench generation, simulation and timing closure. Skills/experience: 3-5 years of industry experience Verilog, SystemVerilog knowledge is essential Knowledge of an Operating System: UNIX / LINUX / Solaris Knowledge of C and PERL is preferred Must have completed atleast one front-end design cycle Should definitely have Synthesis (Synopsys DC) and Simulation(Verilog-XL/NC or VCS) tool knowledge Sound Digital Design Fundamentals is essential Knowledge of microprocessors is also essential Domain knowledge in related areas of work say PCIe, PCI/-X, Ethernet, AXI, USB etc. Â
Responsibilities: Verification of Design - Bug Fixing, Test Plans Coding of Design / Behavioral Models - Delivering Unit Design Synthesis of Design on Target foundries Evaluating New tools (Synthesis / Simulation / Code Coverage etc.)  Human Face: Excellence in Teamwork Guide people on Technical front Go the Extra Mile to get the work resolved Creative and able to think laterally Able to handle last minute changes in work plans Educational Qualifications: Bachelor of Engineering in Electronics or Electrical Science. / M. Sc. (Electronics) Location: New Delhi   |
| Last Updated on Monday, 20 July 2009 02:57 |
